1. Field of the Invention
The present invention relates to a complementary metal-oxide-semiconductor (CMOS) transistor and a method of manufacturing the CMOS transistor. More particularly, the present invention relates to a CMOS transistor employing metal having a desired work function for a gate pattern of the CMOS transistor and a method of manufacturing the CMOS transistor.
2. Description of the Related Art
Recently, a gate insulating layer of a complementary metal-oxide-semiconductor (CMOS) transistor is required not only to maintain a thin equivalent oxide thickness (EOT), but also to sufficiently reduce a leakage current generated between a gate conductive layer and a channel region. Accordingly, a material having a high dielectric constant has been used for the gate insulating layer of the CMOS transistor.
However, when a gate conductive layer including polysilicon is formed on the gate insulating layer including the material having a high dielectric constant, a Fermi-level pining phenomenon is frequently generated. As a result, a behavior of impurities is impeded by the above phenomenon and, thus, a flat band voltage represented by a proportional function of a threshold voltage is not efficiently controlled.
However, research results concerning a formation of the gate conductive layer using a metal to sufficiently reduce the Fermi-level pining phenomenon have been reported recently. The gate conductive layer including the metal sufficiently prevents an increase in the EOT due to a poly-depletion effect frequently generated at the gate conductive layer formed from polysilicon.
Accordingly, the gate pattern of the CMOS transistor has a structure including the gate insulating layer and the gate conductive layer. The gate insulating layer includes the material having the high dielectric constant. The gate conductive layer includes the metal. Here, the metal used for the gate conductive layer includes a metal for adjusting a work function and another metal used for an upper electrical line.
In addition, the CMOS transistor includes an n-typed metal-oxide-semiconductor (NMOS) transistor and a p-typed metal-oxide-semiconductor (PMOS) transistor. Here, a work function of the metal used for the NMOS transistor and a work function of another metal used for the PMOS transistor need to be different from each other.
Accordingly, the metal having the work function of about 4.0 eV to about 4.3 eV is used for a gate pattern in the NMOS transistor. The metal having the work function of about 4.7 eV to about 5.0 eV is used for a gate pattern in the PMOS transistor. This is because when the metal having the work function of about 4.0 eV to about 4.3 eV is used for a gate pattern in the NMOS transistor, the threshold voltage is effectively controlled. Similarly, this is because when the metal having the work function of about 4.7 eV to about 5.0 eV is used for a gate pattern in the PMOS transistor, the threshold voltage is effectively controlled.
To form each source/drain of the NMOS transistor and the PMOS transistor, impurities are implanted at a surface of a semiconductor substrate. A thermal treatment is then performed to activate behavior of the impurities. Here, the thermal treatment is performed at a high temperature of about 1,000° C.
However, when the thermal treatment is performed, the work function of the metal used for the gate conductive layer in the CMOS transistor is frequently changed. All of the metal having the work function of about 4.0 eV to about 4.3 eV in the NMOS transistor and the metal having the work function of about 4.7 eV to about 5.0 eV in the PMOS transistor are changed into a state having a work function of about 4.5 eV after the thermal treatment is performed. This is because the metal adjusting the work function that is used for the gate conductive layers of the NMOS transistor and the PMOS transistor is easily reacted with the metal used for the electrical line during the thermal treatment.
When the work function of the metal used for the gate conductive layer is changed to an undesired value, it becomes difficult to control the threshold voltage. In addition, the thermal treatment for activating the behavior of the impurities may not be omitted in manufacturing process of the CMOS transistor. Thus, there are limits to use the metal having an adequate work function for the gate conductive layer of the CMOS transistor.